Pam data communication with reflection cancellation

ABSTRACT

The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a communication system that removes reflection signals. A digital data stream is processed through both tentative path and the main path. The tentative path uses a first DFE device and a reflection cancellation circuit to generate a correction signal for removing reflection signal from the digital data stream. A second DFE device removes ISI and other noises from the corrected digital data stream. There are other embodiments as well.

CROSS-REFERENCES TO RELATED APPLICATIONS

This patent application is related to U.S. patent application Ser. No.13/791,201, filed 8 Mar. 2013, titled “OPTICAL COMMUNICATION INTERFACEUTILIZING CODED PULSE AMPLITUDE MODULATION”, which claims priority fromU.S. Provisional Patent Application No. 61/714,543, filed 16 Oct. 2012,titled “100G PA CODED MODULATION”, and U.S. Provisional PatentApplication No. 61/699,724, titled “ADAPTIVE ECC FOR FLASH MEMORY”, allof which are incorporated by reference herein for all purposes.

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH AND DEVELOPMENT

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BACKGROUND OF THE INVENTION

The present invention is directed to data communication systems andmethods.

Over the last few decades, the use of communication networks exploded.In the early days Internet, popular applications were limited to emails,bulletin board, and mostly informational and text-based web pagesurfing, and the amount of data transferred was usually relativelysmall. Today, Internet and mobile applications demand a huge amount ofbandwidth for transferring photo, video, music, and other multimediafiles. For example, a social network like Facebook processes more than500 TB of data daily. With such high demands on data and data transfer,existing data communication systems need to be improved to address theseneeds.

Over the past, there have been many types of communication systems andmethods. Unfortunately, they have been inadequate for variousapplications. Therefore, improved communication systems and methods aredesired.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to data communication systems andmethods. More specifically, embodiments of the present invention providea communication system that removes reflection signals. A digital datastream is processed through both tentative path and the main path. Thetentative path uses a first DFE device and a reflection cancellationcircuit to generate a correction signal for removing reflection signalfrom the digital data stream. A second DFE device removes ISI and othernoises from the corrected digital data stream. There are otherembodiments as well.

According to an embodiment, the present invention provides acommunication system. The system includes an input receiver device forreceiving an analog data stream. The system also includes an analog todigital converter (ADC) device coupled to the input receiver device. TheADC device is configured to convert the analog data stream to a digitaldata stream. The digital data stream comprises a first signal and afirst noise profile associated with the first signal. The first noiseprofile includes inter-symbol interference (ISI) noise signals andreflection signals. The system also includes a feed forward equalizer(FFE) device coupled to the ADC device and configured to a tentativesignal path and a main signal path. The system additionally includes afirst decision feedback equalizer (DFE) device configured to an outputof the feed forward equalizer device through the tentative signal path.The first DFE is configured to remove at least a first portion of theISI noise signals. The system additionally includes an adder deviceconfigured to connect the tentative signal path and the main signalpath. The system further includes a reflection canceller circuit coupledto the first DFE device and configured to the main signal path throughthe adder device. The reflection canceller circuit is configured toinput a plurality of correction signals. The correction signals areconfigured to cancel a second portion of the ISI noise signal andreflection signal signals traversing through the main signal path. Thesystem also includes an output of an adder device in the adder deviceconfigured to output an intermediary signal. The system additionallyincludes a second DFE device configured to the main signal path andconfigured to output a PAM 4 symbol in digital form. The resulting PAM 4symbol is based on at least the intermediary signal and the digital datastream.

According to another embodiment, the present invention provides acommunication system that includes an input receiver device forreceiving an analog data stream. The system also includes an analog todigital converter (ADC) device coupled to the input receiver device. TheADC device is configured to convert the analog data stream to a digitaldata stream. The digital data stream comprises a first signal and afirst noise profile associated with the first signal. The first noiseprofile includes inter-symbol interference (ISI) noise signals andreflection signals. The system further includes a feed forward equalizer(FFE) device coupled to the ADC device and configured to a tentativesignal path and a main signal path. The system additionally includes afirst decision feedback equalizer (DFE) device configured to an outputof the feed forward equalizer device through the tentative signal path.The first DFE is configured to remove at least a first portion of theISI noise signals. The system further includes an adder deviceconfigured to connect the tentative signal path and the main signalpath. The system also includes a reflection canceller circuit coupled tothe first DFE device and configured to the main signal path through theadder device. The reflection canceller circuit is configured to input aplurality of correction signals. The correction signal is configured tocancel a second portion of the ISI noise signal and reflection signalstraversing through the main signal path. The system further includes anoutput of an adder device in the adder device configured to output anintermediary signal. The system also includes a second DFE deviceconfigured to the main signal path and configured to output a PAM 4symbol in digital form. The resulting PAM 4 symbol is based on at leastthe intermediary signal and the digital data stream. The system alsoincludes a forward error correcting decoder device.

According to yet another embodiment, the present invention provides acommunication system that includes an input receiver device forreceiving an analog data stream. The system includes an analog todigital converter (ADC) device coupled to the input receiver device. TheADC device is configured to convert the analog data stream to a digitaldata stream. The digital data stream comprises a first signal and afirst noise profile associated with the first signal. The first noiseprofile includes inter-symbol interference (ISI) noise signals andreflection signals. The system additionally includes a feed forwardequalizer (FFE) device coupled to the ADC device and configured to atentative signal path and a main signal path. The system furtherincludes a slicer device configured to an output of the feed forwardequalizer device through the tentative signal path. The slicer device isconfigured to remove at least a first portion of the ISI noise signals.The system further includes an adder device configured to connect thetentative signal path and the main signal path. The system additionallyincludes a reflection canceller circuit coupled to the slicer device andconfigured to the main signal path through the adder device. Thereflection canceller circuit is configured to input a plurality ofcorrection signals. The correction signals are configured to cancel asecond portion of the ISI noise signal and the reflection signalstraversing through the main signal path. The system further includes anoutput of an adder device in the adder device configured to output anintermediary signal. The system additionally includes a DFE deviceconfigured to the main signal path and configured to output a PAM 4symbol in digital form. The resulting PAM 4 symbol is based on at leastthe intermediary signal and the digital data stream.

It is to be appreciated that embodiments of the present inventionprovides many advantages over existing solutions. Conventional DFEsusually use feed-forward (open-loop) equalization for the first few (andmost important) taps, which often causes performance loss. In addition,at some implementations/speeds, the loop can be closed with extensivespeculation, many are iteration-bound and unable to close the first fewtaps. Conventional DFEs are difficult to utilize in PAM-4 (or higherorder PAM) based communication systems. For example, conventional PAM-4DFEs implemented in parallel suffer a 4N exponential state increase, andconventional successive approximation PAM-4 DFEs typically have anincreased amount of analog content to carry more approximations forward.In comparison, embodiments of the present invention provide reflectionsignal cancellation that is used in conjunction with DFEs, which offerboth the performance and ease of implementation. In addition,embodiments of the present invention can be used with existingcommunication systems. There are other embodiments as well.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram illustrating a conventional DFE 100. TheFFE 102 processes input data received from a communication channel.

FIG. 2 is a simplified diagram illustrating a reflection signal profile.

FIG. 3 is a simplified diagram illustrating a communication system 300according to an embodiment of the present invention.

FIG. 4 is a simplified diagram illustrating an RC circuit 400 accordingto an embodiment of the present invention.

FIG. 5 is a simplified diagram illustrating a communication system 500according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to data communication systems andmethods. More specifically, embodiments of the present invention providea communication system with a tentative path and a main path. A digitaldata stream is processed through both tentative path and the main path.The tentative path uses a first device and a reflection cancellationcircuit to generate a correction signal for removing reflection signalfrom the digital data stream. A second DFE device removes ISI and othernoises from the corrected digital data stream. There are otherembodiments as well.

As explained above, high speed communication systems and methods areimportant, and improvements of which are desirable. For example,variants of pulse amplitude modulation (PAM) have been used forhigh-speed data communication, where a large amount of data is processedthrough high-speed data communication network. For example, usingmultiple data communication channels, PAM based communication systemscan provide high-transmission speed (up to and over 100 gigabits/s).Using PAM, the message information is encoded in the amplitude of aseries of signal pulses. It is an analog pulse modulation scheme inwhich the amplitudes of a train of carrier pulses are varied accordingto the sample value of the message signal. Demodulation is performed bydetecting the amplitude level of the carrier at every symbol period. Forexample, PAM4, PAM6, PAM8, and other variants of PAMs can be used indata communication.

An important aspect of data communication is error correction.High-speed communication is meaningless if the data are corrupted orlost during the data communication process. Depending on thecommunication link and encoding mechanism, various types of errorcorrection mechanisms can be used. In PAM communication, data aremodulated into symbols and transmitted from a transmitting entity to areceiving entity. The receiving entity extracts data from the receivedsymbols.

Between the transmitting entity and the receiving entity, through whichthe symbols are transmitted, there is a medium or a channel. Forexample, a channel refers to a medium that carries the symbols from thetransmitting entity to the receiving entity. For example, a channel canbe serviced by a wired, wireless, optical, or another media, dependingupon the communication system type. Regardless the type of channel used,symbols are distorted when transmitted through the channel. Morespecifically, when transmitted through a communication channels asubject symbol may have interference with symbols surrounding thesubject symbol. For example, this type of distortion is referred to as“inter-symbol-interference” (ISI).

Over the past, various solutions have been proposed. For example,equalizers are used to remove channel effects, including ISI, from areceived symbol. In a conventional equalizer, a communication channel isfirst estimated, typically using a training sequence. A set of equalizercoefficient is then generated based on the channel estimate. Theequalizer uses the coefficients when extracting data from the symbols.Depending on the implementation, the coefficients can also be used afterdata extraction. Effectively, the coefficients characterize channelcharacteristics for optimal data extraction from the symbols, and theyare updated as needed.

Accuracy of data communication depends on the equalizer performance. Asrate of data communication increases (moving up to 100 gigabits/s andmore), the importance of equalizers and challenge of implementationthereof grew. For example, in certain high-speed data communicationapplications, a large number (e.g., 30 or more) feed-forward equalizers(FFE) are need to implement a decision feedback equalizer (DFE).

FIG. 1 is a simplified diagram illustrating a conventional DFE 100. TheFFE 102 processes input data received from a communication channel. Inaddition to the actual data that are to be processed, the FFE 102 alsoreceives noise that is bundled with the data. For example, the noisesthat are bundled with the data can be attributed to communication link,interference, ISI, and other sources. As shown in FIG. 1, the decisionblock 104 generates an output that is based on both the FFE 102 and thefeedback equalizer (FBE) 106. The FBE 106, similar to FFE 102, has itsown set of coefficients. By using the outputs of both FFE 102 and theFBE 106, the decision block 104 is effectively using both current inputand past decisions to generate a corrected output value, and thecoefficients assign the weight assigned to current input and pastdecisions.

An important aspect of the DEF 100 is thus to compute the coefficientsfor the FFE 102 and the FBE 106. Objectives in determining thecoefficients are to minimize noises and errors. For example, there havebeen various methods in computing the coefficients in the past, such asCholesky decomposition method, and others.

Unfortunately, conventional techniques have been inadequate. Forexample, in addition to ISI, there are also various types ofdisturbances, such as reflection signals and ISI. For example,reflection signals can be attributed to impedance mismatch where asignal carrying data is not damped out, but instead leaves reflectionsignal. It is to be appreciated that embodiments of the presentinvention efficiently remove reflection signal, as described below.

The following description is presented to enable one of ordinary skillin the art to make and use the invention and to incorporate it in thecontext of particular applications. Various modifications, as well as avariety of uses in different applications will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to a wide range of embodiments. Thus, the present inventionis not intended to be limited to the embodiments presented, but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

In the following detailed description, numerous specific details are setforth in order to provide a more thorough understanding of the presentinvention. However, it will be apparent to one skilled in the art thatthe present invention may be practiced without necessarily being limitedto these specific details. In other instances, well-known structures anddevices are shown in block diagram form, rather than in detail, in orderto avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which arefiled concurrently with this specification and which are open to publicinspection with this specification, and the contents of all such papersand documents are incorporated herein by reference. All the featuresdisclosed in this specification, (including any accompanying claims,abstract, and drawings) may be replaced by alternative features servingthe same, equivalent or similar purpose, unless expressly statedotherwise. Thus, unless expressly stated otherwise, each featuredisclosed is one example only of a generic series of equivalent orsimilar features.

Furthermore, any element in a claim that does not explicitly state“means for” performing a specified function, or “step for” performing aspecific function, is not to be interpreted as a “means” or “step”clause as specified in 35 U.S.C. Section 112, Paragraph 6. Inparticular, the use of “step of” or “act of” in the Claims herein is notintended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

Please note, if used, the labels left, right, front, back, top, bottom,forward, reverse, clockwise and counter clockwise have been used forconvenience purposes only and are not intended to imply any particularfixed direction. Instead, they are used to reflect relative locationsand/or directions between various portions of an object.

As mentioned above, embodiments of the present invention removereflection signal. For example, embodiments of the present invention areused in PAM-4 communication, and reflection cancellation is implementedin conjunction with DFEs and/or slicers, which remove other types ofnoises as well.

FIG. 2 is a simplified diagram illustrating a reflection signal profile.As shown in FIG. 2, a wave form carries a signal at the region 201. Thereflection signal is shown at the region 202. Since the reflectionsignals often cascades and oscillates over a relative extended period oftime, removing reflection signals can be a computationally expensiveprocess. In addition, multiple FFEs are often needed for the first fewtaps, which may result in performance loss. To remove or cancelreflection using FFEs, a large number of FFEs are needed. For example,30 or more FFEs may be required to remove reflection signals. As anexample, reflection signals refer to undesirable signals that are oftenundesirable results of ISI. Depending on the device implementation andthe actual usage, the amount of power required by the large number ofFFEs can be large and impractical.

It is thus to be appreciated that embodiments of the present inventionremove reflection signals efficiently, and with relatively ease ofimplementation in terms of both hardware and methods thereof. Forexample, by using specific reflection cancellation unit, the need formultiple FFEs is eliminated, and a relatively smaller device size can beachieved.

FIG. 3 is a simplified diagram illustrating a communication system 300according to an embodiment of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. As an example, thecommunication system 300 is implemented as a part of a PAM-4communication system, but it is to be understood that otherimplementations and applications are possible as well.

As shown in FIG. 3, an input receiver device 301 is configured forreceiving an analog data stream. For example, the analog data streamcomprises PAM data that is in an analog form for the purpose oftransmission over the communication channel. The PAM data can be in PAM4 format, PAM 2, PAM 8, or other types of PAM formats. According to animplementation, the input receiver device 301 comprises an opticalcommunication interface, through which a large amount of data can bereceived at a high speed (e.g., 40 gigabits or higher). For example, theoptical communication interface includes photo-detector, transimpedanceamplifier (TIA), and other components for quickly processing a largeamount of data.

The analog data stream is processed by an analog to digital converter(ADC) device 302 coupled to the input receiver device. Among otherfeatures, the ADC device 302 is configured to convert the analog datastream to a digital data stream at a relatively high speed. For example,the ADC device 302 can be implemented using SARs, flash ADC, and/orother types of ADC devices. The ADC device 302 is capable of processingdata at a high speed, which is equal to or greater than the datatransfer speed for receiving data at the input receiver device. Thedigital data stream comprises both signals and noises. According tovarious embodiments, the signals are encoded with PAM symbols (e.g., PAM4 symbols). In addition to the symbols from which actual data can beextracted, the digital data stream also includes noises. As explainedabove, noises include both ISI noise signals and reflection signals. Forexample, the profile of reflection signals is illustrated in FIG. 2.

The digital data stream generated by the ADC device 302 is processed bythe FFE device 303. For example, the FFE device 303 is a part of the DFElogic that removes ISI noises. Among other things, the FFE devicesinclude one or more multipliers that are updated according tocharacteristics of the communication channel through which the datastream is received. The FFE device 303 is connected to a tentative datapath 320 and a main data path 330. The tentative data path 320 includesthe DFE device 304 and reflection cancellation (RC) circuit 305. Forexample, tentative data path 320 is specifically configured to removereflection signals (e.g., ISI noise) from the digital data stream. Themain data path 330, which includes the adder device 306 and the DFE 307,is configured to remove ISI noises after reflection signals is cancelledat the adder device 306.

As a part of the tentative data path 320, the DFE device 304 isconfigured to remove at least a portion of the ISI noises. For example,the DFE device 304 uses the outputs from the FFE device 303 to determinevarious characteristics of the communication channels, and using thesecharacteristics, the DFE device 304 is able to remove ISI noises.Depending on the implementation, the DFE device 304 can move other typesof noises as well.

As a part of the tentative data path 320, the main objective of the DFEdevice 304 and the RC circuit 305 is to remove the reflection signals.Since the DFE device 304 removes the ISI noises (or most of it) from theFFE 303 output, the RC circuit 305 is primarily configured to generatinga correction signal. Depending on the implementation, the RC circuit 305may also remove residual ISI noises from the output of the DFE device304. The output of the RC circuit 305 is coupled to the adder 306. Forexample, the correction signal is based on the what is determined by theRC circuit 305 as the reflection signals, and a negative reflectionsignal added to the data stream (e.g., by the adder device 306)effectively removes the reflection signals.

FIG. 4 is a simplified diagram illustrating an RC circuit 400 accordingto an embodiment of the present invention. This diagram is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications. The RC circuit 400 includes input 421 and input 401.The input 421 provides a preliminary determination of reflection. Incertain embodiments, the input 421 selects between an SLC input and aPAM DFE input. For example, the SLC input comprises a slicer forprocessing PAM signals. Depending on the implementation, the signalinput into the RC circuit 400 can be processed by other types of signalprocessing modules in addition to the slicer and DEF. For example, thePAM 4 DFE corresponds to the DFE 304 in FIG. 3, which can be implementedusing slicer (SLC) circuit instead. In various embodiments, both DFE andSLC circuits are used for reflection signal cancellation, and dependingon the specific need, a selection is made between the DFE and the SLCcircuits. The input 401 provides a reference signal. For example, thereference signal from the input 401 comprises an FFE signal output(e.g., from FFE 303 in FIG. 3) that is delay for three (or other numberof) cycles.

The input 402 provides a signal to the duobinary squelcher 409. Forexample, the output of the input 420 comprises a tentative decision fromthe output of the SLC and/or DFE circuits. The duobinary squelcher 409is specifically configured to remove Nyquist errors. For example, a DFEmodule, operating as a preliminary error detector, is often prone toNyquist errors (e.g., oscillating between positive and negative values).As preliminary detectors, such as DFE for PAM4, often suffer from errorpropagation, it is to be appreciated that the addition of the duobinarysquelcher 409 helps mitigate error propagation for preliminary DFE tofinal DFE. It is to be appreciated that other types of error removaltechniques may be used in lieu or in combination of duobinary squelcher409 to remove Nyquist errors.

The output of the duo binary squelcher 409 is processed by D^(N) module407, where N is selected from 2, 4, 8, and 16, which corresponds to PAMmodulation. For example, N affects the amount of delay in removingreflection signals. If N is zero, the reflection cancellation isperformed right away with no delay; when N is large, the reflectioncancellation starts late. For example, if N is zero, reflectioncancellation process starts during the time 203 to cancel reflectionsignals that are near the actual signal 201; if N is large, thereflection cancellation process is delayed (e.g., performed at time204). It is to be appreciated that the N is selected based on thespecific reflection noise characteristic. The least-mean-square (LMS)engine 405 is configured to set up one or more taps for errorgeneration, which is based on the output of the module 407. The errorgenerator device 406 uses the input from the module 407 and the LMSengine 405. According to a specific implementation, the error generatordevice 406 comprises a finite impulse response (FIR) filter. Forexample, one or more taps (e.g., 16 taps) may be needed for the FIRfilter for generating an error signal, which is used for cancellingreflection signals. The output 404 of the RC circuit 400 is laterprovided to the DFE in the main signal line.

Now referring back to FIG. 3. The adder device 306 receives signals fromboth the FFE device 303 and the RC circuit 305. The data signalsdirectly from the FFE device 303 going into the main path 330 includeboth ISI noises and reflection signals. With the correction signals fromthe RC circuit 305, the adder device 306 removes reflection signals fromthe data signals from the FFE device 303. The output data signals of theadder device 306 still include noises, but mostly ISI noises, asreflection signals have been removed using the correction signals.

The DFE device 307, as a part of the main signal path 330, removes theISI noises from the data signals. It is to be appreciated that sincemost, if not all, of the reflection signals are removed using thecorrection signals, the DFE device 307 can better remove ISI and/orother noises, as reflection signals are no longer an issue and ISInoises are “isolated”. For example, the coefficients of the FFE device303 and the DFE device 307 are calculated mainly based on the channelcharacteristics that attribute to ISI noises, the reflection signals areessentially isolated from this calculation. In various implementations,the output of the DFE device 307 comprises PAM symbols (e.g., PAM 4symbols) in digital form, which are based on output of the adder device306 and the data stream. For example, the DFE device 307 comprises a PAM4 slicer input, which includes four discrete levels. Each of the fourdiscrete levels is separated from each other to minimize error rateamong the four discrete levels.

The communication system 300 additionally includes a decoder device 308,which is configured for removing burst errors from the PAM symbols indigital form. For example, the decoder device is implemented using a 1+DModulo-n Decoder. In a specific embodiment, the decode device 308 is a1+D Modulo 4 Decoder. In certain implementations, the decoder device 308is not used, as decoding may be performed by other components.

An FEC device 309 is coupled to the decoder device 308, which performsforward error correction on PAM symbols from the decoder device 308. Asmentioned above, it is to be understood that the decoder device 308 isnot used in certainly implementation, as the DFE 307 may performdecoding. For example, the PAM symbols from the decoder device 308 havebeen processed by the communication system 300 to have reflectionsignal, ISI noise, and burst errors removed through various componentsdescribed above. The FEC device 309 is configured to provide forwarderror correction according to a predetermined coding algorithm, such asBCH code, RS code, and others.

The FEC device 309 is coupled to the PAM driver 310. For example, thePAM driver 310 comprises a PAM transmitter device for transmitting theprocessed signals.

Depending on the implementation, the communication system 300 mayinclude other components as well. For example, the communication system300 includes a PAM 4 receiver device, which can be characterized as aserializer/deserializer (SerDes) device. According to variousembodiments, the PAM 4 transmitter device and the PAM 4 receiver deviceare integrated on a single integrated circuit device, which includes aplurality of CMOS device. For example, each of the CMOS devices has adesign rule of 28 nm and less. In certain embodiments, each of the CMOSdevices has a design rule of 16 nm and less using a FINFET process.

FIG. 5 is a simplified diagram illustrating a communication system 500according to an embodiment of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. In FIG. 5, an inputreceiver device 501 is configured for receiving an analog data stream.For example, the analog data stream comprises PAM data that is in ananalog form for the purpose of transmission over the communicationchannel. The PAM data can be in PAM 4 format, PAM 8, or other types ofPAM formats. According to an implementation, the input receiver device301 comprises an optical communication interface, through which a largeamount of data can be received at a high speed (e.g., 40 gigabits orhigher). For example, the optical communication interface includesphoto-detector, transimpedance amplifier (TIA), and other components forquickly processing a large amount of data.

The analog data stream is processed by an analog to digital converter(ADC) device 502 coupled to the input receiver device. Among otherfeatures, the ADC device 502 is configured to convert the analog datastream to a digital data stream at a relatively high speed. For example,the ADC device 502 can be implemented using SARs, flash ADC, and/orother types of ADC devices. The ADC device 502 is capable of processingdata at very high speed, which is equal to or greater than the datatransfer speed for receiving data at the input receiver device. Thedigital data stream comprises both signals and noises. According tovarious embodiments, the signals are encoded with PAM symbols (e.g., PAM4 symbols). In addition to the symbols from which actual data can beextracted, the digital data stream also includes noises. As explainedabove, noises include both ISI noise signals and reflection signalsignals. For example, the profile of reflection signal signals isillustrated in FIG. 2.

The digital data stream generated by the ADC device 302 is processed bythe FFE device 503. For example, the FFE device 503 is a part of the DFElogic that removes ISI noises. Among other things, the FFE deviceincludes one or more multipliers that are updated according tocharacteristics of the communication channel through which the datastream is received. The FFE device 503 is connected to a tentative datapath 520 and a main data path 530. The tentative data path 520 includesthe SLC device 504 and reflection cancellation (RC) circuit 505. Forexample, tentative data path 520 is specifically configured to removereflection signals from the digital data stream. The main data path 530,which includes the adder device 506 and the DFE 507, is configured toremove ISI noises after reflection signal is cancelled at the adderdevice 506.

As a part of the tentative data path 520, the SLC device 504 isconfigured to remove at least a portion of the ISI noises. As describedabove, the SLC device 504 may be implemented in conjunction with a DFEdevice, and the output of the SLC device 504 and the DFE device isselected by the RC circuit 305.

As a part of the tentative data path 520, the main objective of the SLC504 and the RC circuit 505 is to remove the reflection signals. The RCcircuit 505 is primarily configured to generating a correction signal.Depending on the implementation, the RC circuit 305 may also removeresidual ISI noises from the output of the SLC device 504. The output ofthe RC circuit 505 is coupled to the adder 506. For example, thecorrection signal is based on what is determined by the RC circuit 505as the reflection signal, and a negative reflection signal added to thedata stream (e.g., by the adder device 506) effectively removes thereflection signal.

The adder device 506 receives signals from both the FFE device 503 andthe RC circuit 505. The data signals directly from the FFE device 503going into the main path 530 include both ISI noises and reflectionsignals. With the correction signals from the RC circuit 505, the adderdevice 506 removes reflection signals from the data signals from the FFEdevice 503. The output data signals of the adder device 506 stillinclude noises, but mostly ISI noises, as reflection signals have beenremoved using the correction signals.

The DFE device 507, as a part of the main signal path 530, removes theISI noises from the data signals. It is to be appreciated that sincemost, if not all, of the reflection signals are removed using thecorrection signals, the DFE device 307 can better remove ISI and/orother noises, as reflection signals are no longer an issue and ISInoises are “isolated”. For example, the coefficients of the FFE device503 and the DFE device 507 are calculated mainly based on the channelcharacteristics that attribute to ISI noises, the reflection signals areessentially isolated from this calculation. In various implementations,the output of the DFE device 507 comprises PAM symbols (e.g., PAM 4symbols) in digital form, which are based on output of the adder device306 and the data stream. For example, the DFE device 507 comprises a PAM4 slicer input, which includes four discrete levels. Each of the fourdiscrete levels is separated from each other to minimize error rateamong the four discrete levels.

The communication system 500 additionally includes a decoder device 508,which is configured for removing burst errors from the PAM symbols indigital form. For example, the decoder device is implemented using a 1+DModulo-n Decoder. In a specific embodiment, the decode device 308 is a1+D Modulo 4 Decoder. In various implementations, the decoder device 508is not used, as the DFE 507 may be used to perform decoding.

An FEC device 509 is coupled to the decoder device 508, which performsforward error correction on PAM symbols from the decoder device 508. Forexample, the PAM symbols from the decoder device 508 have been processedby the communication system 500 to have reflection signal, ISI noise,and burst errors removed through various components described above. TheFEC device 509 is configured to provide forward error correctionaccording to a predetermined coding algorithm, such as BCH code, RScode, and others.

The FEC device 509 is coupled to the PAM driver 510. For example, thePAM driver 510 comprises a PAM transmitter device for transmitting theprocessed signals.

Depending on the implementation, the communication system 500 mayinclude other components as well. For example, the communication system500 includes a PAM 4 receiver device, which can be characterized as aserializer/deserializer (SerDes) device. According to variousembodiments, the PAM 4 transmitter device and the PAM 4 receiver deviceare integrated on a single integrated circuit device, which includes aplurality of CMOS device. For example, each of the CMOS devices has adesign rule of 28 nm and less. In certain embodiments, each of the CMOSdevices has a design rule of 16 nm and less using a FINFET process.

It is to be appreciated that embodiments of the present inventionprovides many advantages over existing solutions. Conventional DFEsusually use feed-forward (open-loop) equalization for the first few (andmost important) taps, which often causes performance loss. In addition,at some implementations/speeds, the loop can be closed with extensivespeculation, many are iteration-bound and unable to close the first fewtaps. Conventional DFEs are difficult to utilize in PAM-4 (or higherorder PAM) based communication systems. For example, conventional PAM-4DFEs implemented in parallel suffer a 4N exponential state increase, andconventional successive approximation PAM-4 DFEs typically haveincreasing analog content to carry more approximations forward. Incomparison, embodiments of the present invention provide reflectionsignal cancellation that is used in conjunction with DFEs, which offerboth the performance and ease of implementation. In addition,embodiments of the present invention can be used with existingcommunication systems. There are other embodiments as well.

While the above is a full description of the specific embodiments,various modifications, alternative constructions and equivalents may beused. Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. A communication system, the system comprising: aninput receiver device for receiving an analog data stream; an analog todigital converter (ADC) device coupled to the input receiver device, theADC device being configured to convert the analog data stream to adigital data stream, the digital data stream comprising a first signaland a first noise profile associated with the first signal, the firstnoise profile including inter-symbol interference (ISI) noise signalsand reflection signals; a feed forward equalizer (FFE) device coupled tothe ADC device and configured to be connected/coupled to a tentativesignal path and a main signal path; a first decision feedback equalizer(DFE) device configured to be connected/coupled to an output of the feedforward equalizer device through the tentative signal path, the firstDFE being configured to remove at least a first portion of the ISI noisesignals; an adder device configured to connect the tentative signal pathand the main signal path; a reflection canceller circuit coupled to thefirst DFE device and configured to be connected/coupled to the mainsignal path through the adder device, the reflection canceller circuitbeing configured to input a plurality of correction signals, thecorrection signals being configured to cancel a second portion of theISI noise signal and reflection signal signals traversing through themain signal path; the adder device configured to output an intermediarysignal; and a second DFE device coupled to an output of the adder deviceand configured to output a PAM 4 symbol in digital form in response toreceiving the intermediary signal.
 2. The system of claim 1 wherein thefirst DFE device comprises a PAM-4 one-tap DFE device.
 3. The system ofclaim 1 further comprising a forward error correcting decoder devicecoupled to the 1+D Modulo 4 Decoder.
 4. The system of claim 1 whereinthe reflection canceller circuit comprises: a reflection cancellerfilter device; an error generation device, and a least means squareengine.
 5. The system of claim 1 wherein the reflection cancellercircuit comprises: a reflection canceller filter device; an errorgeneration device; and a least means square engine; wherein thereflection canceller filter device is configured to remove aninterference using a tentative decision from an output of the first DFEafter passing through a duo binary squelcher device coupled to thereflection canceller filter device.
 6. The system of claim 1 wherein thereflection canceller circuit comprises: a reflection canceller filterdevice; an error generation device; and a least means square engine;wherein: the reflection canceller filter device is configured to removean interference using a tentative decision from an output of the firstDFE after passing through a duo binary squelcher device coupled to thereflection canceller filter device, the least means square engine isconfigured to set a tap of the reflection canceller filter device. 7.The system of claim 1 wherein the reflection canceller circuitcomprises: a reflection canceller filter device; an error generationdevice; and a least means square engine; wherein: the reflectioncanceller filter device is configured to remove an interference using atentative decision from an output of first DFE device after passingthrough a duo binary squelcher device coupled to the reflectioncanceller filter device, the least means square engine is configured toset a tap of the reflection canceller filter device, the error generatordevice configured to take an output of the feed forward equalizer deviceand compares the output of the FFE device to the output of the first DFEdevice to generate an error signal for the least means square engine toadapt the tap of the reflection canceller filter device.
 8. The systemof claim 1 wherein the second DFE device comprises a PAM 4 slicer input,the slicer input comprising four discrete levels, each of the fourdiscrete levels being separated from each other to minimize error ratebetween the levels.
 9. The system of claim 1 wherein the PAM 4 symbol isincluded in a PAM 4 receiver device.
 10. The system of claim 9 whereinthe PAM 4 receiver device is characterized as a SERDES device.
 11. Thesystem of claim 9 further comprising a PAM 4 transmitter device.
 12. Thesystem of claim 11 wherein the PAM 4 transmitter device and the PAM 4receiver device are integrated on a single integrated circuit device,the single integrated circuit device comprising a plurality of CMOSdevice, each of the CMOS devices having a design rule of 28 nm and less.13. The system of claim 12 wherein the PAM 4 transmitter device and thePAM 4 receiver device are integrated on a single integrated circuitdevice, the single integrated circuit device comprising a plurality ofCMOS device, each of the CMOS devices having a design rule of 16 nm andless using a FINFET process.
 14. A communication system, the systemcomprising: an input receiver device for receiving an analog datastream; an analog to digital converter (ADC) device coupled to the inputreceiver device, the ADC device being configured to convert the analogdata stream to a digital data stream, the digital data stream comprisinga first signal and a first noise profile associated with the firstsignal, the first noise profile including inter-symbol interference(ISI) noise signals and reflection signals; a feed forward equalizer(FFE) device coupled to the ADC device and configured to beconnected/coupled to a tentative signal path and a main signal path; afirst decision feedback equalizer (DFE) device configured to beconnected/coupled to an output of the feed forward equalizer devicethrough the tentative signal path, the first DFE being configured toremove at least a first portion of the ISI noise signals; an adderdevice configured to connect the tentative signal path and the mainsignal path; a reflection canceller circuit coupled to the first DFEdevice and configured to be connected/coupled to the main signal paththrough the adder device, the reflection canceller circuit beingconfigured to input a plurality of correction signals, the correctionsignals being configured to cancel a second portion of the ISI noisesignal and reflection signals traversing through the main signal path;the adder device configured to output an intermediary signal; a secondDFE device coupled to an output of the adder device and configured tooutput a PAM 4 symbol in digital form, in response to receiving theintermediary signal; and a forward error correcting decoder device. 15.The system of claim 14 wherein the reflection canceller circuitcomprising a reflection canceller filter device, an error generationdevice, and a least means square engine.
 16. The system of claim 14 thereflection canceller circuit comprises: a reflection canceller filterdevice; an error generation device; and a least means square engine;wherein the reflection canceller filter device is configured to removean interference using a tentative decision from an output of the firstDFE after passing through a duo binary squelcher device coupled to thereflection canceller filter device.
 17. The system of claim 14 whereinthe reflection canceller circuit comprises: a reflection cancellerfilter device comprising a finite impulse response filter; an errorgeneration device; and a least means square engine.
 18. A communicationsystem, the system comprising: an input receiver device for receiving ananalog data stream; an analog to digital converter (ADC) device coupledto the input receiver device, the ADC device being configured to convertthe analog data stream to a digital data stream, the digital data streamcomprising a first signal and a first noise profile associated with thefirst signal, the first noise profile including inter-symbolinterference (ISI) noise signals and reflection signals; a feed forwardequalizer (FFE) device coupled to the ADC device and configured to beconnected/coupled to a tentative signal path and a main signal path; aslicer device configured to be connected/coupled to an output of thefeed forward equalizer device through the tentative signal path, theslicer device being configured to remove at least a first portion of theISI noise signals; an adder device configured to connect the tentativesignal path and the main signal path; a reflection canceller circuitcoupled to the slicer device and configured to be connected/coupled tothe main signal path through the adder device, the reflection cancellercircuit being configured to input a plurality of correction signals, thecorrection signals being configured to cancel a second portion of theISI noise signal and the reflection signals traversing through the mainsignal path; the adder device configured to output an intermediarysignal; and a DFE device coupled to an output of the adder deviceconfigured to output a PAM 4 symbol in digital form in response toreceiving the intermediary signal.
 19. The system of claim 18 whereinthe reflection canceller circuit comprises a finite impulse responsefilter for removing the reflection signals.